1. Field of Invention
The present invention relates to a method of forming inter-metal dielectric (IMD). More particularly, the present invention relates to a method of forming inter-metal dielectric using an oxide material that has a fluidic property.
2. Description of Related Art
As the level of integration of semiconductor devices in integrated circuit increases, a silicon wafer has insufficient surface area to accommodate all the necessary interconnects. Therefore, in order to prepare for the large increase in the number of interconnects resulting from the shrinkage of metal-oxide-semiconductor (MOS) transistors, designs having two or more metallic layers must be employed. However, the metallic layers have to be separated from each other by an inter-metal dielectric layer so that unnecessary short-circuiting is prevented. It can be seen that the properties, quality and planarity of the inter-metal dielectric layer are very important factors contributing to the overall quality of the MOS device.
There are two conventional methods of forming an inter-metal dielectric layer for w-via process. The first method uses a spin-on-glass (SOG) layer together with a sacrificial layer, both of which must be etched back. The second method uses deposition of spin-on-glass layer followed by a chemical-mechanical polishing (CMP) operation.
FIGS. 1A through 1C are cross-sectional views showing the progression of manufacturing steps taken to fabricate an inter-metal dielectric layer according to a conventional method that uses a spin-on glass layer and a sacrificial layer, both of which must be etched back.
First, as shown in FIG. 1A, a semiconductor substrate 10 with MOS devices (not shown) formed on it is provided. Next, a metallic layer 12 is formed over the substrate 10, and then the metallic layer 12 is patterned using photolithographic and etching operations. Thereafter, the quality of the patterned metallic layer 12 is checked in an after etching inspection (AEI). In the subsequent step, a conformal dielectric layer 14 is formed over the metallic layer 12. The conformal dielectric layer 14 can be an oxide layer formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) method. Next, a spin-on-glass layer 15 is coated on top of the dielectric layer 14. Two or three spin-coating operations are necessary to coat the spin-on glass layer 15 onto the dielectric layer 14, in order to obtain the desired uniformity and thickness for the spin-on-glass layer 15. Finally, the spin-on-glass layer 15 has to be cured so that its density is increased and a structural form close to that of silicon dioxide (SiO.sub.2) is obtained.
Next, as shown in FIG. 1B, the spin-on-glass layer 15 is etched back to form a spin-on-glass layer 15a, and then the spin-on-glass layer 15a is doped using, for example, ion implantation. Thereafter, a dielectric layer 16 is formed over the spin-on-glass layer 15a. The dielectric layer 16 can be an oxide layer formed using, for example, plasma-enhanced chemical vapor deposition. Subsequently, a sacrificial layer 17, preferably made from a dielectric material, is formed over the dielectric layer 16. Next, the sacrificial layer 17 is etched back so that a highly planarized sacrificial layer 17a is formed as shown in FIG. 1C. The dielectric layer 14, the spin-on-glass layer 15a and the dielectric layer 16 together constitute an inter-metal dielectric layer.
Finally, the inter-metal dielectric layer is patterned to form via holes. Since that part of fabrication is not directly related to the formation of an inter-metal dielectric layer, details are omitted here.
One major defect of the above conventional method is that the spin-on-glass layer has to be formed in 2 to 3 spin-coating operations. Furthermore, two etching back operations have to be conducted. Hence, it takes longer to complete manufacturing.
FIGS. 2A and 2B are cross-sectional views showing the progression of manufacturing steps taken to fabricate an inter-metal dielectric layer according to a conventional method that uses a CMP-planarized, spin-on glass layer.
First, as shown in FIG. 2A, a semiconductor substrate 20 having MOS devices (not shown) formed on it is provided. Next, a metallic layer 22 is formed over the substrate 20, and then the metallic layer 22 is patterned using photolithographic and etching operations. Thereafter, the quality of the patterned metallic layer 22 is checked in an after etching inspection (AEI). In the subsequent step, a conformal dielectric layer 24 is formed over the metallic layer 22. The conformal dielectric layer 24 can be an oxide layer formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) method. Next, a spin-on-glass layer 25 is coated on top of the dielectric layer 24. Two or three spin-coating operations are necessary to coat the spin-on-glass layer 25 onto the dielectric layer 24, in order to obtain the desired uniformity and planarity for the spin-on-glass layer 25. Finally, the spin-on-glass layer 25 has to be cured so that its density is increased and a structural form close to that of silicon dioxide (SiO.sub.2) is obtained.
The spin-on-glass layer 25 is then etched back. Alternatively, the next operation is directly carried out without etching the spin-on-glass layer 25 as shown in FIG. 2A. Next, the spin-on-glass layer 25 is doped using, for example, ion implantation. Thereafter, a dielectric layer 26 is formed over the spin-on-glass layer 25. The dielectric layer 26 can be an oxide layer formed, for example, by plasma-enhanced chemical vapor deposition.
Next, as shown in FIG. 2B, the dielectric layer 26 is planarized by chemical-mechanical polishing to form a dielectric layer 26a. The dielectric layer 24, the spin-on-glass layer 25 and the dielectric layer 26a together constitute an inter-metal dielectric layer.
Finally, the inter-metal dielectric layer is patterned to form via holes. Since that part of fabrication is not directly related to the formation of an inter-metal dielectric layer, details are omitted here.
In the second method, the spin-on-glass layer still has to be formed in 2 to 3 spin-coating operations. Besides that, the dielectric layer 26 for CMP is thicker than non-CMP process. Furthermore, although the number of etching back operations is reduced, chemical-mechanical polishing equipment is expensive, and therefore increases production cost.
In addition, after a patterned photoresist layer is used to form openings in the inter-metal dielectric layer, the spin-on-glass layer absorbs moisture when the photoresist layer is subsequently removed. The moisture absorbed by the spin-on-glass layer is released in a subsequent metallization process, causing outgassing. Outgassing leads to via hole poisoning, which can make deposition of metal particularly difficult and may result in unexpected open-circuit conditions. Moreover, mechanical strength of conventional spin-on-glass material is rather low, and hence may easily form cracks.
In light of the foregoing, there is a need to provide an improved method of forming inter-metal dielectric layer.